Semiconductor device, semiconductor chip and method of manufacturing the semiconductor device

ABSTRACT

Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.15/448,215 filed on Mar. 2, 2017, which claims priority from KoreanPatent Application No. 10-2016-0051528, filed on Apr. 27, 2016 in theKorean Intellectual Property Office, the disclosures of which areincorporated herein in their entirety by reference.

BACKGROUND

Apparatuses and methods consistent with exemplary embodiments relate toa semiconductor device, a semiconductor chip, and a method ofmanufacturing the semiconductor device.

A semiconductor chip may be fabricated using a die-sawing process forcutting a semiconductor wafer on which integrated chips are formed.During a die-sawing process, a saw blade cuts the semiconductor waferalong with a scribe lane region to physically separate a plurality ofsemiconductor chips.

As integrated circuit devices that have large capacity and are highlyintegrated have been required, an area occupied by the scribe laneregion on the semiconductor wafer is being reduced, and risk of damagingintegrated circuits is increasing due to stress applied to semiconductordevices during the die-sawing process.

SUMMARY

One or more exemplary embodiments provide a semiconductor device capableof preventing stress generated during a die-sawing process from beingtransferred to integrated circuits.

Further, one or more exemplary embodiments provide a semiconductor chiphaving an improved reliability.

Further still, one or more exemplary embodiments provide a method ofmanufacturing a semiconductor device, capable of preventing stressgenerated during a die-sawing process from being transferred tointegrated circuits.

According to an aspect of an exemplary embodiment, there is provided asemiconductor device including: a semiconductor substrate including amain chip area and a scribe lane area adjacent to the main chip area,the scribe lane area including a first region adjacent to the main chiparea and a second region adjacent to the first region; an insulatinglayer disposed on the semiconductor substrate; first embossingstructures disposed on a first surface of the insulating layer in afirst area of the insulating layer corresponding to the first region ofthe scribe lane area; second embossing structures disposed on the firstsurface of the insulating layer in a second area of the insulating layercorresponding to the second region of the scribe lane area; and damstructures provided in the first area of the insulating layer atpositions corresponding to the first embossing structures, the damstructures extending in a direction perpendicular to a second surface ofthe insulating layer that is adjacent to the semiconductor substrate.

According to an aspect of another exemplary embodiment, there isprovided a semiconductor device including: a semiconductor substrateincluding a main chip area and a scribe lane area adjacent to the mainchip area; an insulating layer disposed on the semiconductor substrate;embossing structures disposed on a first surface of the insulating layerin an area of the insulating layer corresponding to the scribe lanearea; and wherein trenches are provided in the first surface of theinsulating layer between adjacent embossing structures.

According to an aspect of another exemplary embodiment, there isprovided a semiconductor device including: a semiconductor substratecomprising a main chip area and a scribe lane area adjacent to the mainchip area, the scribe lane area comprising a first region adjacent tothe main chip area and a second region adjacent to the first region; aninsulating layer disposed on the semiconductor substrate; firstembossing structures disposed on a first surface of the insulating layerin a first area of the insulating layer corresponding to the firstregion of the scribe lane area; and second embossing structures disposedon the first surface of the insulating layer in a second area of theinsulating layer corresponding to the second region of the scribe lanearea, wherein each of the first embossing structures have a first shape,each of the second embossing structures have a second shape, and thefirst shape is different from the second shape.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments will be more clearly understood from the followingdetailed description taken in conjunction with the accompanying drawingsin which:

FIGS. 1A to 1C are diagrams of a semiconductor device according to anexemplary embodiment, wherein FIG. 1A is a schematic plan view of asemiconductor device according to an exemplary embodiment, FIG. 1B is aschematic plan view showing an enlarged view of a region denoted by “S”in FIG. 1A, and FIG. 1C is a schematic cross-sectional view of thesemiconductor device taken along a line A-A′ of FIG. 1B;

FIGS. 2A and 2B are schematic diagrams showing an aspect of propagatingcrack generating in a scribe lane region during a die-sawing process;

FIG. 3 is a schematic cross-sectional view of the semiconductor devicetaken along a line A-A′ of FIG. 1B for illustrating a dam structure;

FIG. 4 is a schematic cross-sectional view of the semiconductor devicetaken along a line A-A′ of FIG. 1B for illustrating a dam structure;

FIG. 5 is a plan view of a first embossing pattern in a semiconductordevice according to an exemplary embodiment;

FIG. 6 is a plan view of a first embossing pattern in a semiconductordevice according to an exemplary embodiment;

FIG. 7 is a cross-sectional view of a second region in a semiconductordevice according to an exemplary embodiment;

FIG. 8 is a plan view of a second embossing pattern in a semiconductordevice according to an exemplary embodiment;

FIG. 9 is a schematic perspective view of a part of a dam structure anda first embossing structure in a semiconductor device according to anexemplary embodiment;

FIG. 10 is a cross-sectional view of an embossing pattern and a trenchformed on an insulating layer in a semiconductor device according to anexemplary embodiment;

FIG. 11A is a schematic plan of a semiconductor device according to anexemplary embodiment;

FIG. 11B is a schematic cross-sectional view of the semiconductor devicetaken along a line B-B′ of FIG. 11A;

FIG. 12A is a schematic plan view of a semiconductor device according toan exemplary embodiment;

FIG. 12B is a schematic cross-sectional view of the semiconductor devicetaken along a line C-C′ and a line D-D′ of FIG. 12A;

FIGS. 13A to 13F are cross-sectional views of a method of manufacturinga semiconductor device according to an exemplary embodiment in aprocessing order;

FIGS. 14A and 14B are cross-sectional views of a method of manufacturinga semiconductor device according to an exemplary embodiment; and

FIG. 15 is a cross-sectional view of a semiconductor package accordingto an exemplary embodiment.

DETAILED DESCRIPTION

The inventive concept will now be described more fully with reference tothe accompanying drawings, in which exemplary embodiments of theinventive concept are shown. The inventive concept may, however, beembodied in many different forms and should not be construed as beinglimited to the exemplary embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the concept of the inventive concept tothose skilled in the art. In the drawings, the thicknesses of layers andregions are exaggerated for clarity. Like reference numerals in thedrawings denote like elements, and thus their description will beomitted.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein the term “and/or” includesany and all combinations of one or more of the associated listed items.

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexemplary embodiments only and is not intended to be limiting of theinventive concept. As used herein, the singular forms “a,” “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will be further understood thatthe terms “comprises” and/or “comprising,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of exampleembodiments. As such, variations from the shapes of the illustrations asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, example embodiments should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. Hereinafter, one or a plurality of embodiments combinedthereto may be provided. A terminology “substrate” used herein maydenote a substrate itself, or a stack structure including a substrateand predetermined layers or films formed on a surface of the substrate.

A semiconductor device and a semiconductor chip described hereinaftermay have various structures, and necessary components are only providedas examples herein and one or more embodiments are not limited thereto.As used herein, the term “and/or” includes any and all combinations ofone or more of the associated listed items. Expressions such as “atleast one of,” when preceding a list of elements, modify the entire listof elements and do not modify the individual elements of the list.

FIG. 1A to 1C are diagrams of a semiconductor device 100 according to anexemplary embodiment, wherein FIG. 1A is a schematic plan view of thesemiconductor device 100 according to the exemplary embodiment, FIG. 1Bis a schematic plan view showing an enlarged view of a part denoted by“S” in FIG. 1A, and FIG. 1C is a schematic cross-sectional view of thesemiconductor device 100 taken along a line A-A′ of FIG. 1B.

Referring to FIGS. 1A to 1C, the semiconductor device 100 includes asemiconductor substrate 102 including main chip areas MC and scribe laneareas SL, an insulating layer 104 on the semiconductor substrate 102, anembossing pattern 120 disposed on the insulating layer 104 within thescribe lane areas SL, and dam structures 110 disposed in the insulatinglayer 104 within the scribe lane areas SL. Here, the semiconductordevice 100 may be a semiconductor wafer including a plurality ofintegrated circuit devices.

The semiconductor substrate 102 may include a semiconductor material,e.g., silicon (Si). Alternatively, the semiconductor substrate 102 mayinclude a semiconductor element such as germanium (Ge), or asemiconductor compound material such as silicon carbide (SiC), galliumarsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Asanother example, the semiconductor substrate 102 may have asemiconductor on insulator (SOI) structure. The semiconductor substrate102 may include a conductive area, e.g., a well doped with impurities ora structure doped with impurities.

The insulating layer 104 is disposed on a surface of the semiconductorsubstrate 102. The insulating layer 104 may be formed by stacking aplurality of interlayer insulating layers. The insulating layer 104 mayinclude silicon oxide, silicon nitride, or silicon oxynitride, but isnot limited thereto.

As shown in FIG. 1A, the semiconductor device 100 may include the mainchip areas MC and the scribe lane areas SL.

The semiconductor device 100 may include a plurality of main chip areasMC, and neighboring main chip areas MC may be spaced apart from eachother by a scribe lane area SL interposed therebetween. A semiconductordevice may be formed on each of the main chip areas MC. Thesemiconductor device may include a memory device or a logic device. Inaddition, the semiconductor device may include a plurality ofindependent devices of various kinds. The plurality of independentdevices may include various fine electronic devices, e.g., a metal-oxidesemiconductor field-effect-transistor (MOSFET) such as a complementarymetal oxide semiconductor (CMOS) transistor, a system large scaleintegration (LSI), an image sensor such as a CMOS imaging sensor (CIS),a microelectromechanical system (MEMS), an active device, and a passivedevice.

Each of the scribe lane areas SL may be disposed between adjacent mainchip areas MC, and may surround each main chip area MC. The scribe lanearea SL may be cut by a saw blade (BL of FIG. 2A) while a die-sawingprocess is performed.

The scribe lane area SL may include a first region P1 surrounding andadjacent to edges of the main chip area MC, and a second region P2surrounding and adjacent to the first region P1. That is, the secondregion P2 may be spaced apart from the main chip area MC by the firstregion P1 interposed therebetween. Here, the first region P1 may be aportion where the saw blade BL does not pass through during thedie-sawing process, and the second region P2 may include a portion wherethe saw blade BL passes through to cut during the die-sawing process.That is, the saw blade BL may cut the semiconductor device 100 alongwith the second region P2.

As the semiconductor substrate 102 and various material layers formed onthe semiconductor substrate 102 are cut due to the die-sawing process,the semiconductor device 100 may be divided into a plurality ofsemiconductor chips 300.

In addition, according to one or more exemplary embodiments, each of thesemiconductor chips 300 may include the main chip area MC and aremaining scribe lane area (RSL of FIG. 15) around the main chip areaMC. Here, the remaining scribe lane area may denote the scribe lane areaSL remaining around the main chip area MC after the die-sawing processis performed with respect to the semiconductor device 100. For example,the remaining scribe lane area may include the first region P1 and apart of the second region P2 adjacent to the first region P1.

As shown in FIG. 1C, the embossing pattern 120 may be disposed on theinsulating layer 104 within the scribe lane area SL. The embossingpattern 120 may include first and second embossing structures 122 and124 protruding from an upper surface of the insulating layer 104. Theembossing pattern 120 may include, for example, aluminium or analuminium alloy, but are not limited thereto.

Trenches 125 may be formed on exposed parts of the insulating layer 104between adjacent first and second embossing structures 122 and 124 ofthe embossing pattern 120. In some exemplary embodiments, the trench 125may be formed by removing a part of the insulating layer 104, by usingthe embossing pattern 120 as an etching mask. The trench 125 may have adepth extending from bottom surfaces of the embossing structures 122 and124 toward a lower surface of the insulating layer 120. In someexemplary embodiments, the embossing pattern 120 may include a firstembossing pattern 121 including the first embossing structures 122arranged within the first region P1 and a second embossing pattern 123including the second embossing structures 124 arranged within the secondregion P2.

The dam structures 110 may be disposed in the insulating layer 104within the scribe lane areas SL. The dam structures 110 may extend froma lower surface of the insulating layer 104 in a thickness direction ofthe insulating layer 104 (for example, a third direction D3). Inaddition, the dam structures 110 may discontinuously surround the edgesof the main chip area MC. The dam structures 110 may be arranged with atleast the embossing pattern 120 in the thickness direction of theinsulating layer 104 (e.g., the third direction D3). For example, thedam structures 110 may include a conductive material.

FIGS. 2A and 2B are schematic diagrams of an aspect of propagatingcracks CR generating in the scribe lane area SL during the die-sawingprocess.

Referring to FIGS. 1A, 2A, and 2B, the saw blade BL cuts the insulatinglayer 104 and the semiconductor substrate 102 in direction from theupper surface of the insulating layer 104 toward the lower surface ofthe insulating layer 104. While the saw blade BL cuts the semiconductordevice 100 along with the scribe lane areas SL, stress is generated dueto physical friction between the saw blade BL and the insulating layer104. Such a stress causes crack CR that propagates within thesemiconductor device 100, and when the crack CR propagates toward themain chip area MC, reliability of the integrated circuits may degrade.

As shown in FIG. 2A, the saw blade BL cuts the semiconductor device 100while proceeding from the upper portion of the insulating layer 104downward, and then, the saw blade BL contacts the embossing pattern 120.Here, the crack CR starting from a periphery of the embossing pattern120 moves along with an interface between the embossing pattern 120 andthe insulating layer 104. Then, the crack CR contacts the trench 125,and the stress may be dispersed and the crack CR may be extinguished.Otherwise, the crack CR may propagates in a depth direction of thetrench 125, that is, the crack CR may not propagate toward the main chiparea MC, but propagates toward a lower portion of the semiconductorsubstrate 102.

As shown in FIG. 2B, the crack CR starting from a portion where the sawblade BL and the insulating layer 104 or the semiconductor substrate 102contact each other and propagating toward the main chip area MC may meetthe dam structure 110. The dam structure 110 may prevent the crack CRfrom propagating toward the main chip area MC.

Referring back to FIG. 1C, the dam structures 110 may extend from thelower surface of the insulating layer 104 to the upper surface of theinsulating layer 104. The dam structures 110 may be aligned in athickness direction of the insulating layer 104 (e.g., the thirddirection D3), and exposed out of the upper portion of the insulatinglayer 104 to connect partially to the embossing pattern 120.

As an exemplary embodiment, the dam structures 110 may each include afirst dummy wiring layer 113 a and a second dummy wiring layer 113 barranged at different height levels in the insulating layer 104 in orderto form a multi-layered dummy wiring layer, a first dummy via 115 aconnecting the dummy wiring layers to each other, a second dummy via 115b connecting the second dummy wiring layer 113 b, that is, an uppermostlayer between the multi dummy wiring layers, to the first embossingstructure 122, and a dummy via contact 111 extending from the lowersurface of the insulating layer 104 and connected to the first dummywiring layer 113 a that is a lowermost layer among the multi wiringdummy layers.

Also, the dam structure 110 may include a support pattern connected to alower portion of the dummy via contact 111 to support the dummy viacontact 111. In some exemplary embodiments, the support pattern may beembedded in the semiconductor substrate 102, but is not limited thereto.That is, the support pattern may protrude from a surface of thesemiconductor substrate 102. The support pattern may include, forexample, polysilicon, but is not limited thereto.

In addition, FIG. 1C exemplarily shows that the dam structure 110includes the dual dummy wiring layers 113 a and 113 b, but one or moreembodiments are not limited thereto. That is, the dam structure 110 mayinclude more than two layers, e.g., four or eight dummy wiring layers.Alternatively, the dam structure 110 may include a single dummy wiringlayer.

FIGS. 3 and 4 are schematic cross-sectional views of a semiconductordevice 100 taken along a line A-A′ of FIG. 1B, for illustrating damstructures 110 a according to an exemplary embodiment.

Referring to FIG. 3, the dam structures 110 a extend from the lowersurface of the insulating layer 104, and may be spaced apart from theupper surface of the insulating layer 104 by a predetermined distance.Accordingly, the dam structures 110 a may be separate from the embossingpattern 120.

For example, each of the dam structures 110 a may include only the dummyvia contact 111 extending from the lower surface of the insulating layer104 to a predetermined height, as shown in FIG. 3. However, the damstructures 110 a are not limited to the above example. That is, unlikethe example shown in FIG. 3, the dam structures 110 a may each furtherinclude at least one of the first dummy wiring layer 113 a, the firstdummy via 115 a, and the second dummy wiring layer 113 b illustrated inFIG. 1C.

Referring to FIG. 4, dam structures 110 b may include first damstructures 110_1 extending from the lower surface to the upper surfaceof the insulating layer 104, and second dam structures 110_2 extendingfrom the insulating layer 104 and spaced apart a predetermined distancefrom the upper surface of the insulating layer 104. The first damstructures 110_1 are connected at least partially to the embossingpattern 120, but the second dam structures 110_2 may be spaced apartfrom the embossing pattern 120.

In some exemplary embodiments, the first dam structures 110_1 may becloser to the main chip area MC than the second dam structures 110_2.

Referring back to FIGS. 1A to 1C, the embossing pattern 120 may includethe first embossing pattern 121 having the plurality of first embossingstructures 122 and the second embossing pattern 123 having the pluralityof second embossing structures 124.

The first embossing pattern 121 may be arranged within the first regionP1 of the scribe lane area SL, and may be adjacent to and at leastpartially surround the edge of the main chip area MC. Also, the secondembossing pattern 123 may be arranged within the second region P2 of thescribe lane area SL, and may be adjacent to surround the first embossingpattern 121. That is, the second embossing pattern 123 may be spacedapart from the main chip area MC by the first embossing pattern 121interposed therebetween.

In some exemplary embodiments, the first embossing structures 122configuring the first embossing pattern 121 and the second embossingstructures 124 configuring the second embossing pattern 123 may havedifferent shapes from each other. For example, a length in which thefirst embossing structure 122 extends along the edge of the main chiparea MC (for example, an extending length of the first embossingstructure 122 in the first direction D1) may be longer than a length inwhich the second embossing structure 124 extends along the edge of themain chip area MC (for example, an extending length of the secondembossing structure 124 in the first direction D1).

The first embossing structure 122 configuring the first embossingpattern 121 may be formed as a line extending along the edge of the mainchip area MC, or a bar having a longer axis in the edge direction of themain chip area MC.

The second embossing structure 124 configuring the second embossingpattern 123 may be formed as a dot or rectangle.

In addition, in some exemplary embodiments, the first embossingstructure 122 and/or the second embossing structure 124 may have aninclined side surface. That is, the first embossing structure 122 and/orthe second embossing structure 124 may have a shape that becomesnarrower in a height direction.

In addition, the plurality of first embossing structures 122 each havingthe line shape or the bar shape extending along the edge of the mainchip area MC may be arranged along the edge of the main chip area MC tobe spaced apart from one another, and may discontinuously surround themain chip area MC. Also, the plurality of first embossing structures 122are arranged in a direction away from the edge of the main chip area MC,and thereby surrounding the main chip area MC in layers.

The plurality of second embossing structures 124 each having the dotshape are arranged along the edge of the main chip area MC, and at thesame time, arranged in a direction away from the main chip area MC. Forexample, the plurality of second embossing structures 124 may bearranged as a matrix.

FIG. 5 is a plan view of the first embossing pattern 121 of thesemiconductor device according to an exemplary embodiment.

Referring to FIG. 5 and FIG. 1A, the plurality of first embossingstructures 122 are arranged along the edge of the main chip area MC(e.g., the first direction D1), and may be arranged in a directionperpendicular to the edge of the main chip area MC (e.g., the seconddirection D2). The first embossing structures 122 adjacent to each otherin the first direction D1 are spaced apart a predetermined distance fromeach other in the first direction D1, and the first embossing structures122 adjacent to each other in the second direction D2 may be spacedapart a predetermined distance from each other. The first embossingstructures 122 surround the main chip area MC in layers, and maydiscontinuously surround the edge of the main chip area MC.

In addition, the first embossing structures 122 that are adjacent toeach other in a direction perpendicular to the edge of the main chiparea MC (e.g., the second direction D2) may be arranged to be offset inthe direction along the edge of the main chip area MC (e.g., the firstdirection D1) as much as a first distance x1. Then, the first embossingstructures 122 may be arranged in the second direction D2 in the form ofstairs.

When three first embossing structures 122 that are offset apredetermined distance in the first direction D1 and arranged in thesecond direction D2 form a group, the first embossing structures 122 maybe arranged in the first direction D1 and the second direction D2 whileforming a plurality of groups. For example, first embossing structuresof a first group G1 and first embossing structures of a second group G2may be arranged in the second direction D2, and the first embossingstructures of a third group G3 and the first embossing structures of afourth group G4 may be arranged in the second direction D2. Also, thefirst embossing structures of the first group G1 and the first embossingstructures of the third group G3 may be arranged in the first directionD1, and the first embossing structures of the second group G2 and thefirst embossing structures of the fourth group G4 may be arranged in thefirst direction D1.

Here, three first embossing structures 122 are offset in the firstdirection to form one group, but the number of the first embossingstructures 122 forming one group is not limited thereto.

FIG. 6 is a plan view of a first embossing pattern 121 a of asemiconductor device according to an exemplary embodiment.

Referring to FIG. 6 and FIG. 1A, the first embossing pattern 121 a mayinclude first embossing structures 122 b that are bent around a cornerof the main chip area MC, i.e., at a portion adjacent to a corner of themain chip area MC.

The first embossing structures 122 b having bent shape may not beprovided at every corner of the main chip area MC, but may be providedat some of the corners of the main chip area MC.

FIG. 7 is a cross-sectional view of the second region P2 in thesemiconductor device according to an exemplary embodiment.

Referring to FIG. 7, the second embossing structures 124 may be arrangedat edge portions P2_e of the second region P2, except a center portionP2_c of the second region P2. Here, the edge portions P2_e of the secondregion P2 may denote regions adjacent to boundaries between the firstregion P1 and the second region P2. That is, opposite sides of thecenter portion P2_c in the second region P2 may contact the edgeportions P2_e of the second region P2.

A blade region may denote a region that is directly cut by the saw bladeBL during performing the die-sawing process. In some exemplaryembodiments, the blade region may include the center portion P2_c of thesecond region P2 and some parts of the edge portions P2_e, which areadjacent to the center portion P2_c of the second region P2. In otherwords, a width BL_w of the blade region may be greater than a width ofthe center portion P2_c of the second region P2.

Accordingly, while the die-sawing process is performed, the saw blade BLcuts the semiconductor device 100 along the center portion P2_c of thesecond region P2. Here, opposite sides of the saw blade BL contact thesecond embossing structures 124, and a center portion of the saw bladeBL may directly cut the insulating layer 104 without contacting thesecond embossing structures 124.

Since the second embossing structures 124 are not arranged at the centerportion P2_c of the second region P2, wherein the saw blade BL mainlycontacts the center portion P2_c, generation of particles that aregenerated when the second embossing structures 124 are damaged may bereduced.

FIG. 8 is a plan view of a second embossing pattern 123 a of asemiconductor device according to an exemplary embodiment.

Referring to FIG. 8, the second embossing structures 124 forming thesecond embossing pattern 123 a may be formed as dots. Here, adjacentones of the second embossing structures 124 may be arranged to be offsetfrom one another in the second direction, i.e., in zig-zag pattern,unlike in FIG. 1B. That is, the second embossing structures 124 may bearranged in a zig-zag pattern in the first direction D1. Alternatively,the second embossing structures 124 may be arranged in zig-zag patternalong the second direction D2.

FIG. 9 is a schematic perspective view of a part of the dam structure110 and the first embossing structure 122 of the semiconductor deviceaccording to an exemplary embodiment.

Referring to FIGS. 1A to 1C, and 9, the dam structures 110 are arrangedon the first region P1, and the dam structures 110 and the firstembossing structures 122 may be arranged in a thickness direction of theinsulating layer 104.

In some exemplary embodiments, the first embossing structures 122 mayeach have a line shape or a bar shape extending along the edge of themain chip area MC, and the dam structures 110 disposed under the firstembossing structures 122 may also have line shapes or bar shapesextending along the edge of the main chip area MC.

Here, the dam structure 110 may extend to a first length L1 along theedge of the main chip area MC, and the first length L1 may correspond toan extending length of the first embossing structure 122 along the edgeof the main chip area MC.

FIG. 10 is a cross-sectional view of the embossing patterns and trenches125 formed in an upper portion of the insulating layer 104 in thesemiconductor device according to an exemplary embodiment.

Referring to FIGS. 1C and 10, the first embossing structures 122 or thesecond embossing structures 124 are arranged on the insulating layer104, and the trench 125 may be formed between two adjacent firstembossing structures 122 or two adjacent second embossing structures124.

In some exemplary embodiments, the trench 125 may be formed from theupper surface of the insulating layer 104 to a predetermined depthdownward, and the trench 125 may have a shape that becomes narrowerdownwardly and a rounded end. The trench 125 having the rounded shapemay evenly disperse a crack, and the crack may be removed effectively.

In addition, the first embossing structures 122 or the second embossingstructures 124 may each have a first width w1 in a directionperpendicular to the edge of the main chip area MC (e.g., the seconddirection D2), and the two adjacent first embossing structures 122 orthe two adjacent second embossing structures 124 may be spaced a secondwidth w2 apart from each other.

Here, the first width w1 may denote a width at a bottom surface of thefirst embossing structure 122 or the second embossing structure 124. Thesecond width w2 may denote a distance between the two adjacent first orsecond embossing structures 122 or 124 at the same level as that of thebottom surface of the first embossing structure 122 or the secondembossing structure 124. In some exemplary embodiments, the first widthw1 may be greater than the second width w2. For example, the first widthw1 may be twice as large as the second width w2, but is not limitedthereto.

In addition, referring back to FIGS. 1A to 1C, the trench 125 that isformed by partially removing the insulating layer 104 exposed throughthe embossing pattern 120 may be continuously formed throughout.

Otherwise, in some other exemplary embodiments, the trench 125 may beformed in a certain region of the insulating layer 104.

FIGS. 11A and 11B are diagrams illustrating a semiconductor device 100 caccording to an exemplary embodiment, wherein FIG. 11A is a schematicplan view of the semiconductor device 100 c according to the exemplaryembodiment, and FIG. 11B is a schematic cross-sectional view of thesemiconductor device 100 c taken along a line B-B′ of FIG. 11A.

The semiconductor device 100 c shown in FIGS. 11A and 11B issubstantially the same as the semiconductor device 100 illustrated withreference to FIGS. 1A to 1C, except that the semiconductor device 100 cfurther includes a guard ring structure forming region GR and guard ringstructures 130 arranged in the guard ring structure forming region GR.In FIGS. 11A and 11B, like reference numerals as those of FIGS. 1A to 1Cdenote the same elements, and detailed descriptions thereof are omitted.

Referring to FIGS. 11A and 11B, the scribe lane area SL may include thefirst region P1 and the second region P2, and the first region P1 mayinclude the guard ring structure forming region GR on which the guardring structures 130 are arranged. The guard ring structure formingregion GR may surround edges of the main chip area MC.

The guard ring structures 130 may be arranged between the dam structures110 and the main chip area MC. The guard ring structures 130 maycontinuously surround the edges of the main chip area MC as a ring typeor a loop type.

In FIG. 11B, the guard ring structures 130 surround the edges of themain chip area MC in dual layers, but the number of guard ringstructures 130 is not limited thereto.

The guide ring structures 130 may be arranged in the insulating layer104. The guard ring structures 130 may extend from the lower surface ofthe insulating layer 104 in the thickness direction of the insulatinglayer 104.

In some exemplary embodiments, the embossing pattern 120 may not bedisposed on the guard ring structure forming region GR, in which theguard ring structures 130 are formed.

Alternatively, in some other exemplary embodiments, the first embossingpattern 121 may be formed on the guard ring structure forming region GR,and the first embossing structures 122 may be arranged with the guardring structures 130 in the thickness direction of the insulating layer104. Here, the first embossing structures 122 arranged on the guard ringstructure forming region GR may be continuously formed along the edgesof the main chip area MC like the guard ring structures 130, or may bediscontinuously formed unlike the guard ring structures 130.

In addition, in some exemplary embodiments, the guard ring structures130 may extend from the lower surface of the insulating layer 104 to theupper surface of the insulating layer 104. The guard ring structures 130may be substantially the same as the dam structures 110 shown in FIG.1C. That is, the guard ring structures 130 may each include a dummy viacontact, dummy wiring layers, and a dummy via. However, configurationsof the guard ring structures 130 are not limited thereto, and the guardring structures 130 may be differently configured from the damstructures 110 illustrated with reference to FIG. 1C.

In some other exemplary embodiments, the guard ring structures 130 mayextend from the lower surface of the insulating layer 104, and may bespaced apart by a predetermined distance from the upper surface of theinsulating layer 104. The guard ring structures 130 may include only thedummy via contact, like the dam structures 110 illustrated withreference to FIG. 3. However, configurations of the guard ringstructures 130 are not limited to the above example.

FIG. 12A is a plan view of a semiconductor device 100 d according to anexemplary embodiment, and FIG. 12B is a schematic cross-sectional viewof the semiconductor device 100 c taken along a line C-C′ and a lineD-D′ of FIG. 12A.

The semiconductor device 100 d illustrated with reference to FIGS. 12Aand 12B is substantially the same as the semiconductor device 100illustrated with reference to FIGS. 1A to 1C, except that thesemiconductor device 100 d further includes a passivation layer 140. InFIGS. 12A and 12B, like reference numerals as those of FIGS. 1A to 1Cdenote the same elements, and detailed descriptions thereof are omitted.

Referring to FIGS. 12A and 12B, the semiconductor device 100 d mayfurther include the passivation layer 140 formed on the insulating layer104 and covering at least partially the embossing pattern 120. In someexemplary embodiment, the passivation layer 140 may include a materialthat is different from that of the insulating layer 104. For example,the passivation layer 140 may include a silicon nitride layer.

In some exemplary embodiments, the passivation layer 140 may be onlyformed partially on the scribe lane area SL. Accordingly, thepassivation layer 140 may cover a part of the embossing pattern 120, andexpose another part of the embossing pattern 120.

Here, the trench 125 may not be formed in the portion of the insulatinglayer 104, where the passivation layer 140 is formed. That is, thetrench 125 may be formed in the portion of the insulating layer 104,where the passivation layer 140 is not formed.

FIGS. 13A to 13F are cross-sectional views illustrating a method ofmanufacturing a semiconductor device according to an exemplaryembodiment in a processing order. In FIGS. 13A to 13F, the method ofmanufacturing the semiconductor device 100 illustrated with reference toFIGS. 1A to 1C will be described as an example. FIGS. 13A to 13F showthe scribe lane area SL and the main chip area MC in the semiconductordevice 100.

Referring to FIG. 13A, a semiconductor substrate 102 includes the scribelane areas SL and the main chip areas MC.

In addition, the dummy via contacts 111 are formed on a surface of thesemiconductor substrate 102 within the scribe lane area SL, and a firstinterlayer insulating layer 104 a filling in a periphery of the dummyvia contacts 111 is formed on the surface of the semiconductor substrate102. Also, a via contact 211 and at least one transistor TR are formedon the surface of the semiconductor substrate 102 within the main chiparea MC, and a first interlayer insulating layer 104 a surrounding thevia contact 211 and the transistor TR is formed on the surface of thesemiconductor substrate 102.

In some exemplary embodiments, the dummy via contacts 111 and the viacontact 211 may be formed respectively on support patterns disposedthereunder. The support patterns may be, for example, embedded in thesemiconductor substrate 102, but are not limited thereto. That is, thesupport patterns may protrude from the surface of the semiconductorsubstrate 102. The support pattern may include, for example,polysilicon, but is not limited thereto.

The first interlayer insulating layer 104 a may include silicon oxide,silicon nitride, or silicon oxynitride.

The transistor TR may be obtained by forming a gate electrode structureon the surface of the semiconductor substrate 102 and doping impuritiesin the semiconductor substrate 102 located at opposite sides of the gateelectrode structure.

Also, in some exemplary embodiments, the dummy via contacts 111 arrangedon the scribe lane area SL and the via contact 211 arranged on the mainchip area MC may include metal, metal silicide, semiconductor doped withimpurities, or a combination thereof. For example, the dummy viacontacts 111 and the via contact 211 may include metal such as tungsten,nickel, cobalt, and tantalum, metal silicide such as tungsten silicide,nickel silicide, cobalt silicide, and tantalum silicide, polysilicondoped with impurities, or a combination thereof, but are not limitedthereto.

In addition, a second interlayer insulating layer 104 b is formed on thefirst interlayer insulating layer 104 a throughout the main chip area MCand the scribe lane area SL. The second interlayer insulating layer 104b may include a first dummy wiring layer 113 a disposed on the scribelane area SL, and a first wiring layer 213 a disposed on the main chiparea MC. The first dummy wiring layer 113 a may be connected to thedummy via contacts 111, and the first wiring layer 213 a may beconnected to the via contact 211.

The second interlayer insulating layer 104 b may include silicon oxide,silicon nitride, or silicon oxynitride.

In some exemplary embodiments, in order to form the first dummy wiringlayer 113 a and the first wiring layer 213 a, the second interlayerinsulating layer 104 b covering the first interlayer insulating layer104 a, the dummy via contacts 111, and the via contact 211 is formedover the substrate 102, and the second interlayer insulating layer 104 bis partially removed to form a plurality of openings of line shapes forexposing the dummy via contacts 111 and the via contact 211 through thesecond interlayer insulating layer 104 b. After that, the first dummywiring layers 113 a and the first wiring layer 213 a filling theplurality of openings having the line shape may be respectively formedon the scribe lane area SL and the main chip area MC.

Referring to FIG. 13B, a third interlayer insulating layer 104 c, afourth interlayer insulating layer 104 d, and a fifth interlayerinsulating layer 104 e are sequentially formed on the second interlayerinsulating layer 104 b. The third interlayer insulating layer 104 c mayinclude first dummy vias 115 a on the scribe lane area SL, and mayinclude a first via 215 a on the main chip area MC. The fourthinterlayer insulating layer 104 d may include second dummy wiring layers113 b on the scribe lane area SL, and may include a second wiring layer213 b on the main chip area MC. The fifth interlayer insulating layer104 e may include second dummy vias 115 b on the scribe lane area SL,may include a second via 215 b on the main chip area MC.

In more detail, the third interlayer insulating layer 104 c is formed onthe second interlayer insulating layer 104 b throughout the main chiparea MC and the scribe lane area SL. Openings exposing the first dummywiring layers 113 a and the first wiring layer 213 a are formed in thethird interlayer insulating layer 104 c, and then, the openings arefilled with a conductive material to form the first dummy vias 115 a andthe first via 215 a.

In addition, the fourth interlayer insulating layer 104 d is formed onthe third interlayer insulating layer 104 c throughout the main chiparea MC and the scribe lane area SL. After that, the second dummy wiringlayers 113 b and the second wiring layer 213 b may be formed by adamascene process.

Next, the fifth interlayer insulating layer 104 e is formed on thefourth interlayer insulating layer 104 d throughout the main chip areaMC and the scribe lane area SL. Openings for exposing the second dummywiring layers 113 b and the second wiring layer 213 b are formed in thefifth interlayer insulating layer 104 e, and then, the openings arefilled with a conductive material to form the second dummy vias 115 band the second via 215 b.

The third to fifth interlayer insulating layers 104 c to 104 e mayinclude silicon oxide, silicon nitride, or silicon oxynitride.

In some exemplary embodiments, the dummy via contact 111, the firstdummy wiring layer 113 a, the first dummy via 115 a, the second dummywiring layer 113 b, and the second dummy via 115 b forming each of thedam structures 110 may be formed as lines or bars extending along theedge of the main chip area MC.

Referring to FIG. 13C, a metal layer 120L is formed on the insulatinglayer 104. The metal layer 120L may be formed on both of the scribe lanearea SL and the main chip area MC. For example, the metal layer 120L mayinclude aluminium or an aluminium alloy, but is not limited thereto.

Referring to FIG. 13D, the metal layer 120L is patterned to form theembossing pattern 120 on the scribe lane area SL, and form a landing pad220 on the main chip area MC.

In some exemplary embodiments, referring to FIGS. 13D and 1B, theembossing pattern 120 may include the first embossing pattern 121 formedon the first region P1 and the second embossing pattern 123 formed onthe second region P2. The first embossing structures 122 and the damstructures 110 may overlap with each other in the thickness direction ofthe insulating layer 104.

In some exemplary embodiments, the first embossing structures 122forming the first embossing pattern 121 and the second embossingstructures 124 forming the second embossing pattern 123 may be patternedto have different shapes from each other. For example, lengths in whichthe first embossing structures 122 and the second embossing structures124 extend along the edge of the main chip area MC may be different fromeach other. Otherwise, the first embossing structures 122 may be formedas lines or bars extending along the edge of the main chip area MC, andthe second embossing structures 124 may be formed as dots.

Referring to FIG. 13E, the insulating layer 104 exposed through theembossing pattern 120 is partially removed by using the embossingpattern 120 as an etching mask to form the trenches 125. The trenches125 may extend from the bottom surface of the embossing pattern 120 tothe lower level. In addition, in FIG. 13E, the trench 125 is formed toan upper surface of the fourth interlayer insulating layer 104 d, but isnot limited thereto, that is, a depth of the trench 125 may vary.

Referring to FIG. 13F, the die-sawing process is performed, and thesemiconductor substrate 102 and various material layers formed on thesemiconductor substrate 102 are cut by the saw blade BL. Then, thesemiconductor device may be divided into a plurality of semiconductorchips. Each of the semiconductor chips may include the main chip area MCand the scribe lane area SL remaining on a peripheral portion of themain chip area MC.

Although FIGS. 13A to 13F illustrate that manufacturing processesperformed on the scribe lane area SL and the main chip area MC areperformed at the same time, the manufacturing processes on the scribelane area SL and the main chip area MC may be performed separately.

The method of manufacturing the semiconductor device 100 is describedabove with reference to FIGS. 13A to 13F, but the semiconductor devicesof various structures may be manufactured by modifying the descriptionsprovided with reference to FIGS. 13A to 13F within the technical scopeof the inventive concept.

FIGS. 14A and 14B are cross-sectional views of a method of manufacturinga semiconductor device, according to an exemplary embodiment. FIGS. 14Aand 14B show the scribe lane area SL and the main chip area MC in thesemiconductor device.

Referring to FIG. 14A, the semiconductor device that has undergone theprocesses illustrated with reference to FIGS. 13A to 13D is prepared.

In addition, the passivation layer 140 covering the embossing pattern120 and the landing pad 220 is formed on the insulating layer 104, and amask layer 150 for exposing a part of the passivation layer 140 isformed on the passivation layer 140.

The mask layer 150 exposes a part of the passivation layer 140, wherethe embossing pattern 120 is formed, and a part of the passivation layer140 on the landing pad 220.

The passivation layer 140 may include a material that is different fromthat of the insulating layer 104. For example, the passivation layer 140may include a silicon nitride layer.

Referring to FIG. 14B, the passivation layer 140 exposed through themask layer 150 and the insulating layer 104 under the passivation layer140 may be etched by using the mask layer 150 and the embossing pattern120 as an etching mask. In the scribe lane area SL, the insulating layer104 is partially etched to form the trenches 125 by using the mask layer150 and the embossing pattern 120 as the etching mask. In the main chiparea MC, the passivation layer 140 exposed through the mask layer 150 isremoved to form a pad window 140 w exposing the landing pad 220. Afterthat, the mask layer 150 may be removed.

In some exemplary embodiments for manufacturing the semiconductor device100 d illustrated with reference to FIGS. 12A and 12B, followingprocesses may be performed.

After forming the passivation layer 140 on the insulating layer 104, amask layer for exposing a part of the passivation layer 140 is formed onthe passivation layer 140. Here, the mask layer may be only formed on atleast a part of the embossing pattern 120.

Then, an etching process is performed by using the mask layer as anetching mask. As a result of the etching process, the passivation layer140 exposed through the mask layer and a part of the insulating layer104 under the passivation layer 140 are removed to form the trenches125, and the passivation layer 140 covered by the mask layer and theinsulating layer 104 under the passivation layer 140 may not be etched.After that, the mask layer may be removed.

Exemplary methods of manufacturing the semiconductor device according toone or more exemplary embodiments are described above, but one ofordinary skill in the art would appreciate that the semiconductordevices having various structures obtained through changes andmodifications from the semiconductor devices illustrated with referenceto FIGS. 1A to 12B may be manufactured by applying changes andmodifications within the technical scope of the one or more exemplaryembodiments.

FIG. 15 is a cross-sectional view of a semiconductor package 1000according to an exemplary embodiment.

Referring to FIG. 15, the semiconductor package 1000 may include apackage substrate 1100, a semiconductor chip 1200 mounted on a surfaceof the package substrate 1100, connection members 1300, a molding member1400, and external connection members 1500. The semiconductor chip 1200may be obtained by performing a die-sawing process with respect to thesemiconductor device illustrated with reference to FIGS. 1A to 14B.

The package substrate 1100 may include an upper wiring layer 1110, alower wiring layer 1120, and internal wires 1130 connecting the upperwiring layer 1110 and the lower wiring layer 1120 to each other. Theupper wiring layer 1110 may be connected to a chip pad 1210 via theconnection member 1300, and the lower wiring layer 1120 may be connectedto the external connection member 1500. The upper wiring layer 1110, thelower wiring layer 1120, and the internal wires 1130 may function as amedium for electrically connecting the semiconductor chip 1200 mountedon the package substrate 1100 to an external device, together with theconnection members 1300 and the external connection members 1500.

The semiconductor chip 1200 may include a main chip area on which asemiconductor device is formed on a center portion thereof, and aremaining scribe lane area RSL on a peripheral portion of the main chiparea. Here, the remaining scribe lane area RSL may denote a scribe lanearea that remains on the periphery of the main chip area after thedie-sawing process is performed with respect to the semiconductor deviceon which integrated circuit devices are formed. A dam structure and/oran embossing pattern may be formed on the remaining scribe lane area RSLfor preventing the crack from propagating toward the main chip area.

The semiconductor chip 1200 may be mounted on the surface of the packagesubstrate 1100, and may be electrically connected to the packagesubstrate 1100 via the connection members 1300 disposed between thepackage substrate 1100 and the semiconductor chip 1200. In someexemplary embodiments, the semiconductor chip 1200 may include a memorydevice, a logic device (e.g., a microprocessor, an analog processor, anda digital signal processor), or a system-on-chip for performing variousfunctions. The memory device may include, for example, a dynamic randomaccess memory (DRAM), a static RAM (SRAM), a flash memory, anelectrically erasable and programmable read only memory (EEPROM), aparameter RAM (PRAM), a magnetic RAM (MRAM), or a resistive RAM (RRAM).

Otherwise, the semiconductor chip 1200 may be a multi-chip having astructure in which two or more semiconductor chips are stacked. Forexample, the two or more semiconductor chips may be memory devices ofthe same kind, or one of the two or more semiconductor chips may be amemory device and another may be a micro-controller device.

The connection members 1300 are formed on the upper wiring layer 1110 inorder to electrically connect the semiconductor chip 1200 to the packagesubstrate 1100. The connection member 1300 may include a conductivematerial, copper (Cu), aluminium (Al), solder, silver (Ag), tin (Sn), orgold (Au). For example, the connection member 1300 may be a bumpincluding a solder ball, a solder bump, a metal pillar, and a solder, ora wire formed by a wire bonding device.

In some exemplary embodiments, the integrated circuit device may not beformed on the remaining scribe lane area RSL of the semiconductor chip1200, and thus, the connection members 1300 may include dummy connectionmembers 1300 a disposed under the remaining scribe lane area RSL of thesemiconductor chip 1200. However, in some other exemplary embodiments,the dummy connection members 1300 a may be omitted.

The molding member 1400 may surround the semiconductor chip 1200 on thepackage substrate 1100. The molding member 1400 may include anepoxy-group molding resin or a polyimide-group molding resin.

According to the semiconductor chip 1200 of the one or more exemplaryembodiments, the propagation of the crack generating in the scribe lanearea toward the main chip area during the die-sawing process may beprevented, and thus, degradation in reliability of the integratedcircuit due to the crack may be prevented. Moreover, since thesemiconductor chip 1200 includes the dam structure and/or the embossingpattern on the remaining scribe lane area RSL, damage to the integratedcircuit in the main chip area due to the stress that may be applied tothe semiconductor chip 1200 during assembling the semiconductor package1000 may be prevented.

While exemplary embodiments have been particularly shown and described,it will be understood that various changes in form and details may bemade therein without departing from the spirit and scope of thefollowing claims.

1.-20. (canceled)
 21. A semiconductor device comprising: a semiconductorsubstrate; an insulating layer on the semiconductor substrate; a firstembossing structure on the insulating layer, the first embossingstructure comprising an upper surface having a first width and a lowersurface having a second width greater than the first width; and a damstructure in the insulating layer and below the first embossingstructure, the dam structure comprising a conductive material layerspaced apart from the first embossing structure with a portion of theinsulating layer therebetween.
 22. The semiconductor device of claim 21,wherein the first embossing structure includes a first metal and theconductive material layer includes a second metal, and the first metalis different from the second metal.
 23. The semiconductor device ofclaim 21, wherein the first embossing structure includes aluminum. 24.The semiconductor device of claim 21, wherein the conductive materiallayer includes copper.
 25. The semiconductor device of claim 21, whereinthe insulating layer includes silicon oxide.
 26. The semiconductordevice of claim 21, wherein the dam structure further comprises aconductive via in the portion of the insulating layer, the conductivevia extending from the first embossing structure to the conductivematerial layer.
 27. The semiconductor device of claim 21, furthercomprising a second embossing structure on the insulating layer, whereinthe first embossing structure has a first shape and the second embossingstructure has a second shape, and the first shape is different from thesecond shape.
 28. The semiconductor device of claim 27, wherein thefirst embossing structure has a line shape extending along a directionparallel to the upper surface of the insulating layer.
 29. Thesemiconductor device of claim 27, wherein the second embossing structurehas a dot shape.
 30. A semiconductor device comprising: a semiconductorsubstrate; an insulating layer on the semiconductor substrate; and firstembossing structures on the insulating layer, each of the firstembossing structures comprising an upper surface having a first widthand a lower surface having a second width greater than the first width,wherein trenches are provided in the insulating layer between adjacentones of the first embossing structures.
 31. The semiconductor device ofclaim 30, further comprising dam structures in the insulating layer andbelow the first embossing structures, wherein each of the dam structurescomprises a conductive material layer spaced apart from the firstembossing structures with a portion of the insulating layertherebetween.
 32. The semiconductor device of claim 31, wherein thetrenches extend from a first level of the lower surface of the firstembossing structures to a second level of an upper surface of theconductive material layer.
 33. The semiconductor device of claim 31,wherein each of the dam structures extends from an upper surface of theinsulating layer to a lower surface of the insulating layer.
 34. Thesemiconductor device of claim 31, wherein each of the first embossingstructures includes a first conductive material and the conductivematerial layer includes a second conductive material, and the firstconductive material is different from the second conductive material.35. The semiconductor device of claim 30, wherein the second width ofthe lower surface of the first embossing structures is greater than adistance between adjacent ones of the first embossing structures. 36.The semiconductor device of claim 30, wherein each of the trenches has ashape that becomes narrower downward.
 37. A semiconductor devicecomprising: a semiconductor substrate; an insulating layer on thesemiconductor substrate; first embossing structures on the insulatinglayer, the first embossing structure including a conductive material;and dam structures in the insulating layer and below the first embossingstructures, the dam structures comprising a conductive material layerspaced apart from the first embossing structure with a portion of theinsulating layer therebetween, wherein first trenches are provided inthe insulating layer between adjacent ones of the first embossingstructures, and wherein a width of the conductive material layer issmaller than a width of a lower surface of the first embossingstructures.
 38. The semiconductor device of claim 37, wherein a heightof the conductive material layer is smaller than a height of each of thefirst embossing structures.
 39. The semiconductor device of claim 37,further comprising second embossing structures on the insulating layer,wherein each of the first embossing structures has a first shape andeach of the second embossing structures has a second shape, and thefirst shape is different from the second shape.
 40. The semiconductordevice of claim 39, wherein second trenches are provided in theinsulating layer between adjacent ones of the second embossingstructures.